Digital-to-analog (D/A) converters and their output amplifiers experience power glitches, causing erratic performance in the systems being driven by the D/A converters. For example, control systems driven by these devices can misfire due to power-up glitches occurring before the D/A converter stabilizes to normal operation.
Prior Art FIG. 1 illustrates a simplified prototypical output stage 10 that suffers from such power-up glitches. The output stage 10 includes an operational amplifier 20 driving an output device 30. The output device 30 has a PMOS transistor M3 coupled in parallel with a capacitor CC1, and an NMOS transistor M4 coupled in parallel with a capacitor CC2. The source of the PMOS transistor M3 is directly coupled to a power supply Vdd while the source of the NMOS transistor M4 is coupled to a common ground reference. The output signal of the output stage 10 is generated at the coupling of the drains of the PMOS and NMOS transistors M3 and M4.
During steady-state operation of the output stage 10, the supply voltage Vdd and the bias current I.sub.b provided to the op amp 20 are presumptively valid and the internal circuitry of the output stage 10 can thus achieve a proper state. However, when the bias current is invalid, the state of the internal circuitry of the output stage 10 is uncertain and may not be meaningful. This occurs, e.g., during power-up as the supply voltage Vdd rises to a valid steady state. While Vdd ramps up, bias current I.sub.b exists but is invalid. However, even an invalid supply voltage Vdd can cause the gate of the PMOS transistor M3 to remain low due to device characteristics such as parasitic capacitance. As Vdd rises, a gate to source voltage is generated at the PMOS transistor M3 causing it to turn on.
Prior Art FIG. 2 is a schematic of one particular output stage 10' that helps illustrate one source of the power glitch dilemma. The output stage 10' includes a folded cascode amplifier 22, a class AB control amplifier 24 (or "output quiescent control stage") and output devices 30. An on-chip bias current generator (not shown) provides a bias current I.sub.b and four current mirrors MR1-MR4 amplify and distribute the bias current I.sub.b to the different devices within the output stage 10'. The provision of bias current to the folded cascode amplifier 22 requires that Vdd be sufficient to overcome a two NMOS Vt voltage step down through MR3. In contrast, the provision of bias current to the output devices 30 requires that Vdd be sufficient to overcome a one Vt voltage step down in order to be valid. In essence, the bias current I.sub.b must conduct through four current mirrors before becoming valid at each stage of the output stage 10'. Thus the output devices 30 become active during power-up before the op amp 22 is operating in a valid state.
Certain power glitch problems can be addressed by isolating the output of the internal circuitry from the output of the chip housing the internal circuitry. Prior art techniques have accomplished this through isolation switches controlled by a window comparator that compares the supply voltage Vdd with two fixed comparison thresholds. Specifically, logic outputs from the window comparator control the isolation switches, connecting the chip output either to the internal circuitry output (when the supply voltage is valid) or to a fixed voltage potential. This ensures that the chip output is either valid or set to a known voltage state (e.g., a common ground reference).
The isolation approach of the prior art presents at least three drawbacks. First, since wake up times for bias circuits, amplifiers, and other related circuit devices change with process, voltage and temperature, the comparison thresholds must be set for the worst case scenario. This unnecessarily compromises power up latency for all other scenarios. Second, the isolation switches add additional parasitic effects (e.g., resistance and capacitance) at the output. This can be especially bad in circuits utilizing feedback, as the parasitic effects alter the feedback characteristics. Finally, the isolation switches merely isolate the power glitches and do not eliminate them or prevent related internal problems in any way. For example, large crowbar currents flowing in the internal circuitry typically accompany power glitches. These large crowbar currents can cause the device to latch-up.